The invention relates to a method for reducing dielectric overetch when making contact to conductive features, where those conductive features are interspersed with a dielectric material in a substantially planar surface. The method makes use of etch selectivities between different dielectric materials.
In semiconductor devices, it is known to etch through a dielectric material to make electrical contact to a conductive or semiconductor feature which is covered by the dielectric material. Electrical contact may be made by way of a via, for example, or by formation of a conductor formed by a damascene method.
The etch is ideally aligned with the buried conductive or semiconductor feature. The etchant is generally selective between the dielectric material being etched and the material of the conductive or semiconductor feature, preferentially etching the dielectric material while etching the material of the conductive or semiconductor very slowly or not at all, and thus will stop when the conductive or semiconductor feature is reached. If the etch is misaligned, some portion of the etched region may not fall on the conductive or semiconductor feature, instead continuing into fill dielectric, and excessive overetch may occur in this misaligned region.
Some designs and devices may have particularly limited tolerance for dielectric overetch. There is a need, therefore, to etch through dielectric material to form electrical contacts to buried conductive or semiconductor features without compromising device performance or risking excessive overetch.